Steps to Creating a Windows CE FAL/FMD Driver

This guide is here to help new developers develop a NAND Driver for their platform using the FAL/FMD Driver. Before choosing to write a NAND driver following the FAL/FMD driver model, the developer should first choose whether the MDD/PDD model or FAL/FMD model is more appropriate for their platform and to meet their goals.

Before starting on the driver it would be a good idea to first read and understand the FAL/FMD Model via MSDN Documentation on the FAL/FMD

FAL/FMD Model
The FAL/FMD model is fairly straight forward, you basically need to provide functions to the Windows FAL to Erase a Block, Write a Sector, Read a Sector, Get Block Status and Set Block Status.

When dealing with Block and Sector Numbers with your flash, you should treat all numbers from the FAL to your FMD as Logical Block or Sector Numbers. This will allow you to easily remap and move flash blocks around.

MDD/PDD Model Wrapper for FMD Driver
There is a PDD Wrapper for the MDD/PDD Model that basically creates a PDD that simply calls into an FMD driver. Although this will work fine for existing NAND Flash Drivers, I do not recommend using this method to create a MDD/PDD Model if you do not already have a working and stable FMD Driver.

NAND Chip and Platform Configuration
Before any work on the driver is started, it is important to understand what the NAND Chip in use expects and how it interfaces with the Platform.

All NAND chips have a command based interface where a Command is issued across the data bus, followed by optional Address data and finally actual data. Additional signals which may be needed are Chip Enable, Address Latch Enable and Command Latch Enable. You will also need to determine if your NAND is interleaved or not.

To determine how you interface with your NAND you will need to refer to the Processor Manual, NAND Chip Datasheet and Schematic (or Hardware Engineer responsible for the platform's hardware design.)

Interleaved NAND
My opinion on interleaving NAND is that unless you absolutely need the additional speed or performance that it provides that it adds too much complexity to be worthwhile in the majority of situations.

Looking at Other NAND Drivers
If you are unclear as to how the FAL/FMD system works (after reading through MSDN.) there is a functional NAND driver used by the H4SAMPLE BSP. This is located at: H4SAMPLE\SRC\DRIVERS\NANDFLASH.

Determine Type of ECC to Use
There are a few options that are available when it comes to adding ECC support to NAND. The number of bits of Error Detection / Correction required will generally determine what options are available.

The first option is to use a Hardware ECC Controller, although this is the fastest solution, it requires hardware support to operate. Many (but likely not all) SOC processors that have dedicated support for NAND also have NAND ECC Controllers. Additonally, some hardware solutions only provide support for Single-Bit Correction.

The second option is to use the provided Microsoft ECC Library. This library only supports 512-byte pages and generates a 6-byte ECC code that is capable of 1-bit correction, 2-bit detection. This can still be used on devices with > 512-byte pages, but those pages will have to be broken up into multiple 512-byte sections. Doing so may result in too much ECC data being generated (overflowing the free space in the Spare or OOB section.) so care should be taken before going this route.

The final option is to purchase a third-party ECC Library or create your own.

Both interleaving and MLC NAND causes restrictions to be placed on the type of ECC Algorithm that may be used (due to it's requirement for > 1-bit Correction, 2-bit Detection) so it is important to understand your platforms ECC requirements prior to choosing any particular solution.

SLC versus MLC NAND

This article will hopefully explain many of the important differences between MLC and SLC NAND and how using each may affect a platform.

SLC (Single-Level Cell)
Single-Level-Cell NAND is a type of NAND where each cell (an electrical unit containing a charge) is able to represent two states (either a one or a zero.) In this type of NAND, if a single-cell became corrupted, only a single-bit would change state.

For example, the 8-bit byte 00100110 would require 8 Cells of an SLC NAND chip to store the byte. If a single cell became invalid then only one of the bits would flip from a 0 to a 1 or a 1 to a 0.

MLC (Multi-Level Cell)
Multi-Level Cell NAND is a type of NAND where each cell (an electrical unit containing a charge) is able to represent more than two states (for example 4 states). In this type of NAND if a single cell became corrupted, more than a single bit would change state.

For example (4 State MLC NAND), the 8-bit byte 00100110 would require 4 cells of MLC NAND to store the byte. If a single Cell became invalid then one(1) - two(2) of the bits could flip.

NAND and ECC
NAND Flash itself, is known to suffer from the possibility of having a cell within a Page become corrupt (change to a state other than the correct state.) Because of this ECC is used to determine if any bits have flipped, and if they have correct them (as long as too many haven't flipped.)

Historically, 1-bit Error Correction, 2-bit Error Detection was always used for the ECC Generation because SLC NAND only suffers from single-bit errors on cells that are within a good block (Bad Blocks can have more than one (1) bad cell per page.)

With the advent of MLC NAND, 1-bit Error Correction, 2-bit Error Detection is no longer sufficient to detect NAND errors as a single corrupt cell may actually cause 2 or more bits to flip depending on how many levels each cell could contain (4-state = 2 bits, 8-state = 3 bits, etc...)

Considerations When Deciding on SLC or MLC NAND
MLC NAND often costs less per MB and is available in larger sizes as SLC as it can be made more densely (due to multiple states per cell.) Because of this cost consideration, the use of MLC NAND has become more and more prevalent as our storage needs also increase.

Because using MLC NAND requires the use of an ECC Algorithm that can do better than Single-Bit Error Correction, Double-Bit Error Detection (SECDED) using MLC NAND may cause situations where Hardware ECC Controllers are not able to be used to offload the processor (many only support SECDED.)